1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation. Thereafter, a drive-in step is applied to repair crystalline damage and to drive-in and activate the implanted dopant.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to the gate on which sidewall spacers have been formed. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity heavily doped region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source (unless bidirectional current is used), however lightly doped regions are typically formed for both the source and drain to avoid additional processing steps.
Disadvantages of LDDs include increased fabrication complexity and increased parasitic resistance due to their light doping levels. During operation, LDD parasitic resistance decreases drain current. Linear drain current (i.e., drain current in the linear or triode region) is reduced by the parasitic resistance in both the source and drain. Saturation drain current (i.e., drain current in the saturation region) is largely unaffected by the parasitic resistance of the drain but greatly reduced by the parasitic resistance of the source. Therefore, saturation drain current can be improved while reducing hot carrier effects by providing a lightly doped region only on the drain side. That is, the drain includes lightly and heavily doped regions, and the entire source is heavily doped.
Asymmetrical IGFETs (with asymmetrically doped sources and drains) are known in the art. For instance, U.S. Pat. No. 5,424,229 entitled xe2x80x9cMethod For Manufacturing MOSFET Having An LDD Structurexe2x80x9d by Oyamatsu discloses providing a mask with an opening over a substrate, implanting a dopant through the opening at an angle to the substrate to form a lightly doped drain region on one side without a corresponding source region on the other side, forming a gate in the opening which overlaps the lightly doped drain region, removing the mask, and implanting heavily doped source and drain regions using the gate as an implant mask. As another example, U.S. Pat. No. 5,286,664 entitled xe2x80x9cMethod For Fabricating The LDD-MOSFETxe2x80x9d by Horiuchi discloses forming a gate, implanting lightly doped source and drain regions using the gate as an implant mask, forming a photoresist layer that covers the source side and exposes the drain side, depositing a single spacer on the drain side using liquid phase deposition (LPD) of silicon dioxide, stripping the photoresist, and implanting heavily doped source and drain regions using the gate and single spacer as an implant mask.
A drawback to these and other conventional asymmetrical IGFETs is that the heavily doped source and drain regions typically have identical dopant concentrations. Although the doping concentration of the heavily doped drain region may be constrained in order to reduce hot carrier effects, the doping concentration of the heavily doped source region need not be constrained in this manner. Furthermore, increasing the doping concentration of the heavily doped source region reduces the source-drain series resistance, thereby improving drive current.
Complementary metal-oxide semiconductor (CMOS) circuits typically include adjacent N-channel (NMOS) and P-channel (PMOS) devices. Since CMOS inverter circuits use very little power, CMOS is particularly useful in very large-scale integrated (VLSI) circuits where even small power dissipation in each transistor becomes a problem when thousands or millions of transistors are integrated on a chip. CMOS processes typically use N-well and P-well masks early in the processing sequence to define N-type and P-type active regions. CMOS processes also typically include a single masking step for forming the gates, separate masking steps for implanting lightly doped N-type source/drain regions into the P-type active region and lightly doped P-type source/drain regions into the N-type active region, formation of oxide spacers adjacent to the gates, and then separate masking steps for implanting heavily doped N-type source/drain regions into the P-type active region and heavily doped P-type source/drain regions into the N-type active region.
Accordingly, a need exists for improved asymmetrical N-channel and P-channel IGFETs that reduce both source-drain series resistance and hot carrier effects.
The present invention provides an asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the lightly doped drain region and the heavily doped source region provide channel junctions, and the heavily doped drain region and the ultra-heavily doped source region are spaced from the channel junctions. Advantageously, one or both IGFETs have low source-drain series resistance and reduce hot carrier effects.
By definition, the dopant concentration of the ultra-heavily doped source region exceeds that of the heavily doped source and drain regions, and the dopant concentration of the heavily doped source and drain regions exceeds that of the lightly doped drain region. Furthermore, the heavily doped source and drain regions need not have similar dopant concentrations.
Preferably, both the N-channel and P-channel IGFETs include a source that consists of heavily doped and ultra-heavily doped source regions, and a drain that consists of the lightly doped and heavily doped drain regions. It is also preferred that the dopant concentration of the ultra-heavily doped source regions is in the range of 1.5 to 10 times that of the heavily doped source and drain regions, and the dopant concentration of the heavily doped source and drain regions is in the range of 10 to 100 times that of the lightly doped drain regions, and furthermore that the dopant concentration of the lightly doped drain regions is in the range of about 1xc3x971017 to 5xc3x971018 atoms/cm3, the dopant concentration of the heavily doped source and drain regions is in the range of about 1xc3x971019 to 1xc3x971020 atoms/cm3, and the dopant concentration of the ultra-heavily doped source regions is in the range of about 1.5xc3x971019 to 1xc3x971021 atoms/cm3.
In accordance with an aspect of the invention, a method of making asymmetrical N-channel and P-channel IGFETs includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type adjacent to an isolation region.
Forming a first IGFET includes forming a first gate with first and second opposing sidewalls over the first active region, applying a first ion implantation of second conductivity type to implant first lightly doped source and drain regions into the first active region, applying a second ion implantation of second conductivity type to convert substantially all of the first lightly doped source region into a first heavily doped source region without doping the first lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation of second conductivity type to convert a portion of the first heavily doped source region outside the first spacer into a first ultra-heavily doped source region without doping a portion of the first heavily doped source region beneath the first spacer, and to convert a portion of the first lightly doped drain region outside the second spacer into a first heavily doped drain region without doping a portion of the first lightly doped drain region beneath the second spacer. A first source in the first active region includes the first heavily doped and ultra-heavily doped source regions, and a first drain in the first active region includes the first lightly doped and heavily doped drain regions.
Forming a second IGFET includes forming a second gate with third and fourth opposing sidewalls over the second active region, applying a first ion implantation of first conductivity type to implant second light doped source and drain regions into the second active region, forming third and fourth spacers adjacent to the third and fourth sidewalls, respectively, applying a second ion implantation of first conductivity type to convert a portion of the second lightly doped source region outside the third spacer into a second heavily doped source region without doping a portion of the second lightly doped source region beneath the third spacer, and to convert a portion of the second lightly doped drain region outside the fourth spacer into a second heavily doped drain region without doping a portion of the second lightly doped drain region beneath the fourth spacer, removing at least portions of the third and fourth spacers, and applying a third ion implantation of first conductivity type to convert the second heavily doped source region into a second ultra-heavily doped source region and to convert substantially all of the second lightly doped source region into a third heavily doped source region without doping the second lightly and heavily doped drain regions. A second source in the second active region includes the third heavily doped and the second ultra-heavily doped source regions, and a second drain in the second active region includes the second lightly doped and heavily doped drain regions.
Preferably, the method includes forming an insulating layer over the substrate to provide first, second, third and fourth sidewall insulators adjacent to the first, second, third and fourth sidewalls, respectively, depositing a blanket layer of insulative spacer material on the insulating layer, and applying an anisotropic etch such that first, second, third and fourth insulative spacers are adjacent to the first, second, third and fourth sidewall insulators, respectively. In this manner, the first spacer includes the first sidewall insulator and the first insulative spacer, the second spacer includes the second sidewall insulator and the second insulative spacer, the third spacer includes the third sidewall insulator and the third insulative spacer, and the fourth spacer includes the fourth sidewall insulator and the fourth insulative spacer. Removing at least portions of the third and fourth spacers is accomplished by removing the insulative spacers without removing the sidewall insulators.
Another aspect of the method includes forming the first and second gates, forming a first photoresist layer that covers the second active region, applying the first ion implantation of second conductivity type using the first photoresist layer and the first gate as an implant mask, forming a second photoresist layer that covers the first active region, applying the first ion implantation of first conductivity type using the second photoresist layer and the second gate as an implant mask, forming the insulating layer, forming a third photoresist layer that covers the second active region and the first lightly doped drain region, applying the second ion implantation of second conductivity type using the third photoresist layer and the first sidewall insulator and a portion of the first gate as an implant mask, forming the insulative spacers, forming a fourth photoresist layer that covers the second active region, applying the third ion implantation of second conductivity type using the fourth photoresist layer and the first gate and the first and second spacers as an implant mask, forming a fifth photoresist layer that covers the first active region, applying the second ion implantation of first conductivity type using the fifth photoresist layer and the second gate and the third and fourth spacers as an implant mask, removing the insulative spacers, forming a sixth photoresist layer that covers the first active region and the second lightly and heavily doped drain regions, and applying the third ion implantation of first conductivity type using the sixth photoresist layer and the third sidewall insulator and a portion of the second gate as an implant mask.
These and other aspects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follow.